1. Field of the Invention
The present invention relates to a programmable controller and, more particularly, to a programmable controller having an interrupt control means for, when a plurality of parallel input/output devices (I/Os) generate interrupt processing requests, determining a priority of interrupt processing of each I/O and generating an interrupt vector.
2. Description of the Related Art
A conventional interrupt control method performed by a programmable controller is shown in FIG. 1.
FIG. 1 is a block diagram showing a conventional programmable controller.
Referring to FIG. 1, a central processing unit (CPU) 1 is connected to a random access memory (RAM) 3, a read only memory (ROM) 5, and a basic unit 7 through an internal bus. The CPU 1 performs data processing or interrupt service processing for I/Os 9a, 9b, and 9c.
The RAM 3 has a function as a main memory and is used to store various data. The ROM 5 stores control programs to be executed by the CPU 1. The basic unit has the plurality of I/Os 9a, 9b, and 9c arranged in a daisy chain, an interface circuit 11 for interfacing the CPU 1 with the I/Os 9a, 9b, and 9c, and a data bus 13 for connecting the I/Os 9a, 9b, and 9c and the interface circuit 11. In this case, the I/O 9a located closest to the CPU 1 has the highest priority. The I/Os 9a, 9b, and 9c are connected to the interface circuit 11 through an interrupt request line 15 having a wired-OR arrangement. The interface circuit 11 has an interrupt signal controller 17 and an OR gate 19.
The basic unit 7 is further connected to an extended unit 21 through an extended bus CDATA. Note that only one extended unit 21 is shown in FIG. 1 for illustrative simplicity, but a plurality of extended units can be connected in a daisy chain manner. The basic unit 7 located closest to the CPU 1 has the highest priority, and lower priorities are sequentially assigned to the extended units. Similar to the basic unit 7, the extended unit 21 has a plurality of I/Os 9a, 9b, and 9c, a data bus 13, and an interrupt request line 15. The extended unit 21 further includes an interface circuit 23 connected to the I/Os 9a, 9b, and 9c through the data bus 13. The interface circuit 23 has an interrupt controller 25. The interrupt controller 25 sends interrupt request signals IRP supplied from the I/Os 9a, 9b, and 9c through the interrupt request line 15 to the interface circuit 11 of the basic unit 7. Therefore, the interrupt request signal IRP from the basic unit 7 and the interrupt request signal IRP from the extended unit 21 are ORed by the OR gate 19 and the obtained signal is supplied to the CPU 1 as a CPU interrupt request signal 27.
when the CPU 1 receives the CPU interrupt request signal 27, it outputs an interrupt accept signal INTA to the interface circuit 11. The interrupt signal controller 17 generates an acknowledge signal INTAC at the leading edge of the first interrupt accept signal INTA. If an interrupt request is output from the basic unit 7, the controller 17 outputs an active interrupt enable signal BIEI to the first I/O 9a and an inactive unit interrupt enable signal CIEI to the extended unit 21 in order to accept the interrupt request from the basic unit 7 having the higher priority order than that of the extended unit 21. If the first I/O 9a itself outputs an interrupt request, it outputs an inactive interrupt enable signal BIEO to the second I/O 9b. If the first I/O 9a itself does not output an interrupt request, it outputs an active interrupt enable signal BIEO to the next stage. In the same manner, the interrupt request signal is sequentially transferred to an interrupt request source. When an active interrupt enable signal is transferred to the interrupt request source, an inactive interrupt enable signal BIEO is output to I/Os after the request source.
If no interrupt request is output from the basic unit 7, the interrupt signal controller 17 outputs an active unit interrupt enable signal CIEI to the extended unit 21 in synchronism with the acknowledge signal INTAC. As a result, an interrupt request from the extended unit 21 is accepted.
The interface circuit 23 in each extended unit 21 controls interrupt requests between the extended units 21 and interrupt requests from the I/Os 9a, 9b, and 9c in the extended unit 21. When the interrupt controller 25 in the extended unit 21 receives an active interrupt enable signal CIEI from the basic unit 7, it outputs an I/O interrupt enable signal IEI to the first I/O 9a. If the first I/O 9a itself does not output an interrupt request, it outputs an interrupt enable signal IEO to the second I/O 9b. In the same manner, the interrupt enable signal is sequentially transferred to an I/O of an interrupt request source.
FIG. 2 is a circuit diagram showing in detail the I/O 9a of the interface circuit 23 shown in FIG. 1. Note that circuit arrangements of the other I/Os 9b and 9c are the same as that of the I/O 9a. FIGS. 3A through 3H are timing charts in which: FIG. 3A is a timing chart showing an acknowledge signal INTA; FIG. 3B, an interrupt request signal IRP; FIG. 3C, an interrupt enable signal CIEI for an extended unit; FIG. 3D, a unit interrupt enable signal CIEO; FIG. 3E; an I/O interrupt enable signal IEI; FIG. 3F, a processing request signal INT; FIG. 3G, an output IEO from an AND gate 206; and FIG. 3H, data on a data bus 31.
Referring to FIG. 2, when the I/O 9a, 9b, or 9c in the extended unit 21 is to output an interrupt processing request to the CPU 1, an interrupt request circuit 203 sets a processing request signal INT shown in FIG. 3F to be low active at a timing T1 in accordance with an interrupt factor. The processing request signal INT is output from an output buffer 207 (open collector), wired-ORed, and output onto the interrupt request line 15. The signal on the interrupt request line 15 is fetched by the CPU 1 as an interrupt request signal IRP (FIG. 3B). When the CPU 1 accepts the interrupt request signal IRP, it outputs an interrupt acknowledge signal INTA (FIG. 3A) to the interrupt controller 17 at a timing T2. Since the interrupt request is not from the I/Os 9a, 9b, and 9c of the unit including the interrupt controller 17, the controller 17 outputs an acknowledge signal INTAC to the interrupt controller 25 in the extended unit 21. If the interrupt request signal IRP is active, the interrupt controller 25 sets a unit interrupt accept signal l23 to be active in synchronism with the signal INTAC. At this time, if a unit interrupt enable signal CIEI (FIG. 3C) is active, the controller 25 sets an I/O interrupt enable signal IEI (FIG. 3E) to be active and outputs the enable signal to the I/O 9a, 9b, or 9c which outputs the interrupt request. In this case, if the I/O 9a accepts the interrupt enable signal IEI, for example, an output of an interrupt enable signal IEO (FIG. 3G) to the following I/Os 9b and 9c is disabled. If the I/Os 9a, 9b, and 9c simultaneously output the processing request signals INT, the controller 25 sets an I/O interrupt accept signal l25 to be active in synchronism with the acknowledge signal INTAC. If the I/O interrupt enable signal IEI is active, the I/O 9a sets the following I/Os 9b and 9c in an interrupt disable state at a timing T3 in accordance with the output IEO (FIG. 3G) from the AND gate 206. In addition, the I/O 9a causes an AND gate 205 to set a vector generator 208 to be active to output an interrupt vector (FIG. 3H) onto a data bus. The output vector is fetched by the CPU 1 at a timing T4.
In the above conventional system, however, if the plurality of I/Os 9a, 9b, and 9c in the unit simultaneously set the interrupt request signals IRP to be active with respect to the CPU 1, the I/O interrupt enable signal IEI is set to be active in synchronism with the acknowledge signal INTAC and sequentially transferred from the first I/O 9a. For this purpose, the I/Os must be successively mounted. That is, if a slot not mounting an I/O is present in a circuit or an interrupt enable signal line is disconnected, an interrupt enable signal cannot be supplied to an interrupt request source, and the system is hung up.